Digital Twin MVP — Semiconductor Fab Yield

Automotive MCU (Microcontroller Unit) / Power IC Fab Segment · Capstone Team 4 · Wai, Anand, Vallarino, Mylavarapu

Daily Yield Trend — Baseline (30 days, seed 42)

Defect Mode Pareto (ranked most to least frequent)

Tool Group Health (end of 30-day simulation)

Scenario Controls

SPC (Statistical Process Control) TightnessBaseline (1.0)
Maintenance Frequency1.0x
Inline Inspection Rate10%
What does Re-run do? Increments the seed (42 → 43 → 44…), then re-runs both baseline and scenario with that same new seed. This keeps the random event sequence identical for both runs — so only the operational levers differ. The yield improvement is consistent across seeds (typically +3 to +5 pp for the combined scenario), confirming the result is robust. Current seed: 42

Yield — Baseline vs Scenario

Cycle Time Comparison

Feature Importance — What Drives Yield Most?

Yield Response Surface (Tool Health × Drift)

Prediction Lead Time — Twin Detects Problems ~24 Hours Before Wafer Sort

Surrogate Model Card

Architecture
Calibrated transparent surrogate model
Calibration Basis
Public benchmarks + synthetic simulation data (SECOM, ITRS/IRDS)
Input Features
6 process/tool features per lot
Target Variable
Wafer-level yield (% good die)
Goodness-of-Fit (R²)
0.83 — directional validation against published benchmarks
Prediction Lead Time
~6 steps ≈ ~24 hrs ahead of wafer sort

Defect Mode Pareto — Current Scenario

Daily Scrap Die — Baseline vs Scenario

Defect Mode × Tool Group Affinity Matrix (which machines cause which defects)

Financial Impact Breakdown

Automotive Supply Impact

Implementation Roadmap

Where Every Parameter Comes From

Each major parameter in this simulation is either sourced from published industry standards, benchmarked against public datasets, or transparently calibrated — with the source and rationale documented for every value. The table below shows every parameter, its value, the published range, and the exact source.

Tool GroupMTBF
(Mean Time Between Failures)
MTTR
(Mean Time To Repair)
Process Time
(hrs/lot)
Defect Rate
(per pass)
Drift Rate
(per day)
Lithography120 hrs8 hrs2.5 hrs18%0.6%/day
Etch200 hrs4 hrs1.8 hrs13%0.4%/day
Deposition160 hrs6 hrs3.0 hrs11%0.5%/day
Ion Implant180 hrs5 hrs1.5 hrs8%0.3%/day
CMP140 hrs6 hrs2.0 hrs15%0.6%/day
Metrology300 hrs3 hrs0.8 hrs2%0.1%/day
Published Range100–300 hrs2–10 hrs0.5–4 hrs0.5–20%Model estimate
SourceSEMI E10 semi.org/en/Standards/CTR_031244Semiconductor manufacturing literatureITRS/IRDS irds.ieee.orgTeam calibration

Other Key Assumptions and Their Sources

AssumptionValue We UsedPublished RangeSourceWhy This Value
Base yield (zero defects)92%85–95%ITRS/IRDSRepresentative upper-midrange baseline for mature automotive-node processes (28–90nm); actual midpoint of the range is 90%
Defect impact multiplier0.15 per defectCalibratedTeam calibrationProduces 85–95% yield range matching ITRS benchmarks
Rework success rate75%20–90%IEEE Trans. Semicon. Mfg.Moderately optimistic blended average across defect types
Die per wafer500400–600Industry rule of thumb~5mm × 5mm die on 200/300mm wafer
Lots per month210 (7 lots/day × 30 days)Pilot scopeProject design1 product family; 7 lots/day is consistent with 89,752 + 15,248 = 105,000 die ÷ 500 die/lot = 210 lots
Chip selling price$2.50/die$1–$5IC Insights, Gartner, WSTSMidpoint for automotive MCU ASP
Scrap cost per die$0.80/die$0.50–$1.50IC Knowledge, IBSConservative midpoint of manufacturing cost
MCUs per vehicle85–20+S&P Global MobilityConservative average from teardown analyses
Line downtime cost$1–5M/day$1–5M/dayAutomotive News, McKinseyWidely cited during 2020–2022 chip shortage
SECOM datasetValidation reference93.4% pass rateUCI ML Repositoryarchive.ics.uci.edu/ml/datasets/SECOM

The 4 Formulas Used in the Simulation

These formulas were designed by our team (not copied from a textbook) to capture directional relationships documented in semiconductor yield literature. The constants were determined through calibration: we adjusted values until simulation outputs matched published benchmarks (ITRS 85–95% yield range, SECOM 93.4% pass rate, published defect Pareto rankings).

Formula 1: Risk Score (per tool, per lot)
risk = (1 − health) × 0.5 + drift × 10 + random(0, 0.1)
health = tool condition (1.0 = perfect, 0.5 = degraded). Lower health → higher risk.
drift = accumulated calibration error since last maintenance (typically 0–0.05).
random(0, 0.1) = small noise for day-to-day process variation.
Why 0.5 and 10? Calibrated so that risk ranges from ~0 (healthy tool) to ~0.5 (degraded tool), producing realistic yield variation. Team calibration
Formula 2: Adjusted Defect Rate (per tool, per lot)
adj_rate = base_rate × (1 + risk) × SPC1.5
base_rate = from the tool parameter table above (e.g., 18% for lithography).
(1 + risk) = amplifies defect rate when tool is degraded. At risk=0.5, rate is 1.5× baseline.
SPC1.5 = tighter SPC (lower number) reduces effective defect rate non-linearly. At SPC=0.7: 0.7^1.5 = 0.586 (41% reduction).
Why exponent 1.5? Tested 1.0, 1.5, and 2.0. Exponent 1.0 made SPC too weak; 2.0 was unrealistically strong; 1.5 matched published studies showing SPC accounts for ~15–20% of yield improvement. Team calibration
Formula 3: Lot Yield Calculation (at wafer sort)
yield = 0.92 − Σ(severity × 0.15) + noise(±0.015)
yield = clamp(yield, 0.50, 0.99)
0.92 = base yield with zero defects. From ITRS/IRDS 85–95% range for mature nodes.
severity = random 0–1 per defect (not all defects are equally bad).
0.15 = maximum single-defect impact (15 percentage points). Calibrated so 2–3 defects produce realistic yield drops.
±0.015 = ±1.5 pp random lot-to-lot variation (realistic daily fluctuation).
clamp 50–99% = prevents unrealistic extremes. Team calibration validated against SECOM 93.4%
Formula 4: Tool Drift, Breakdowns & Maintenance
drift += drift_rate / maint_freq
breakdown if: random() < 24 / (MTBF × maint_freq)
maintenance if: hours > MTBF × 0.7 / maint_freq
drift_rate / maint_freq = more frequent maintenance → slower drift accumulation.
Breakdown probability = Poisson process. For lithography: 24/120 = 20% chance per day at baseline. From SEMI E10 standard.
0.7 threshold = maintenance at 70% of MTBF interval = preventive (before expected failure). From SAE JA1011 (Reliability-Centered Maintenance).
On maintenance: health restored +0.3 (partial, not full), hours reset, drift reduced by 0.01.

About the Random Seed

The simulation uses a seeded pseudorandom number generator (Park & Miller, 1988, Communications of the ACM). Every "random" event (breakdowns, defects, process variation) follows a deterministic sequence controlled by the seed number. Seed 42 always produces the exact same results. When you click "Re-run Simulation," the seed increments (42 → 43 → 44…) and both baseline and scenario are re-run with that same seed, ensuring the only difference between the two runs is the operational lever settings — not the random sequence. The yield improvement is consistent across seeds, confirming the result is not a fluke.

Simulation Corrections (v6)

The following corrections were applied in this version relative to the initial prototype:

1. Inspection placement (structural fix): The inline inspection check now runs once per lot (after all tool groups have processed it), not once per tool group. The original code ran the check inside the tool loop, giving a lot up to 6 chances to be inspected per pass — inflating the effective inspection rate from 30% to ~88% at the slider's max position. The corrected implementation matches the intended design: one lot-level inspection check per lot per day.

2. Zero-inspection slider bug: Setting inspection to 0% now correctly disables inspection. The original used p.insp||0.1, which treated 0 as falsy and fell back to 10%. Fixed using p.insp??0.1.

3. Controlled re-run: Clicking Re-run now re-runs both baseline and scenario with the same new seed, ensuring a controlled comparison where only parameters differ.

Note: Due to fix #1, the combined scenario yield improvement in this corrected version will differ from the +5.24 pp figure cited in the project report, which was derived from the earlier prototype. The directional findings remain unchanged.

Complete Source List

SEMI E10 SEMI E10-0422: Equipment reliability metrics (MTBF, MTTR). semi.org/en/Standards/CTR_031244
ITRS/IRDS International Roadmap for Devices and Systems: defect targets, yield ranges. irds.ieee.org
SECOM UCI Machine Learning Repository: 1,567 real wafer records, 591 sensors. archive.ics.uci.edu/ml/datasets/SECOM
Reuters Nexperia chip crisis coverage (Oct–Nov 2025). reuters.com/business/autos-transportation/
IC Insights / Gartner / WSTS Semiconductor pricing and market data. Published annual reports.
IC Knowledge / IBS Semiconductor manufacturing cost models.
S&P Global Mobility (formerly IHS Markit): Automotive semiconductor content per vehicle.
Team Calibration Constants determined by iteratively matching simulation outputs to published benchmarks.